Cespe UnB

Editorial Office:
Management:
R. S. Oyarzabal

Technical Support:
D. H. Diaz
M. A. Gomez
W. Abrahão
G. Oliveira

Publisher by
Knobook Pub






216/168=1.29


1.17

A compact 128/192/256-bits symmetric cryptography hardware module

doi: 10.6062/jcis.2019.10.01.0155

(Free PDF)

Authors

O. de Souza Martins Gomes and R. L. Moreno

Abstract

This article describes the implementation of Twofish - one of the Advanced Encryption Standard (AES) finalists, in Field Programmable Gate Array - FPGA. The core was implemented in Altera Quartus Cyclone board. The code is totally portable and can be used in any FPGA. The algorithm was implemented for 128-bit word and 128, 192 and 256-bit keys. The main goal of this work was the implementation of an efficient, compact and modular Twofish hardware module that can find a wide range of applications as an alternative from AES-Rijndael.

Keywords

Cryptography, Twofish, AES, FPGA, Communication.

Search










Combining wavelets and linear spectral mixture model for MODIS satellite sensor time-series analysis
doi: 10.6062/jcis.2008.01.01.0005
Freitas and Shimabukuro(Free PDF)

Riddled basins in complex physical and biological systems
doi: 10.6062/jcis.2009.01.02.0009
Viana et al.(Free PDF)

Use of ordinary Kriging algorithm and wavelet analysis to understanding the turbidity behavior in an Amazon floodplain
doi: 10.6062/jcis.2008.01.01.0006
Alcantara.(Free PDF)

A new multi-particle collision algorithm for optimization in a high performance environment
doi: 10.6062/jcis.2008.01.01.0001
Luz et al.((Free PDF)

Reviewer Guidelines
(Under Construction)
Advertisers/Sponsors
Advertises Media Information